US 12,032,340 B2
Time-to-digital converter circuitry
Mohammed Abdulaziz, Lund (SE); Henrik Sjöland, Lund (SE); and Tony Påhlsson, Lund (SE)
Assigned to Telefonaktiebolaget LM Ericsson (publ), Stockholm (SE)
Filed by Telefonaktiebolaget LM Ericsson (publ), Stockholm (SE)
Filed on Aug. 21, 2023, as Appl. No. 18/236,222.
Application 18/236,222 is a continuation of application No. 17/910,437, granted, now 11,868,094, previously published as PCT/EP2020/057190, filed on Mar. 17, 2020.
Prior Publication US 2023/0393533 A1, Dec. 7, 2023
Int. Cl. G04F 10/00 (2006.01); H03L 7/081 (2006.01); H03L 7/183 (2006.01)
CPC G04F 10/005 (2013.01) [H03L 7/0818 (2013.01); H03L 7/183 (2013.01)] 19 Claims
OG exemplary drawing
 
1. Time-to-digital converter (TDC) circuitry for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal, the TDC circuitry comprising:
a plurality of constituent TDCs, wherein each constituent TDC is configured to convert a phase difference between a constituent reference signal and a constituent clock signal to a digitally represented constituent output signal;
a reference signal provider configured to provide the respective constituent reference signals to each of the constituent TDCs; and
a digital signal combiner configured to provide the digitally represented output signal based on the digitally represented constituent output signals of the constituent TDCs;
wherein the TDC circuitry is configured to selectively switch between a parallel operation mode, in which the plurality of constituent TDCs operate in a parallel processing fashion using a common constituent clock signal, and at least one of a serial operation mode and one or more intermediate operation modes, the serial operation mode being a mode in which the plurality of constituent TDCs operate in a serial processing fashion and an intermediate operation modes being a mode in which two or more collections of the plurality of constituent TDCs operate in a parallel processing fashion while two or more constituent TDCs within at least one of the two or more collections operate in a serial processing fashion.