US 12,032,259 B2
Array substrate and display panel
Xingwu Chen, Shenzhen (CN); Mei Chen, Shenzhen (CN); Qi Song, Shenzhen (CN); and Dongze Li, Shenzhen (CN)
Assigned to TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 17/440,123
Filed by TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Shenzhen (CN)
PCT Filed Jul. 19, 2021, PCT No. PCT/CN2021/107166
§ 371(c)(1), (2) Date Sep. 16, 2021,
PCT Pub. No. WO2022/267122, PCT Pub. Date Dec. 29, 2022.
Claims priority of application No. 202110687342.5 (CN), filed on Jun. 21, 2021.
Prior Publication US 2024/0036421 A1, Feb. 1, 2024
Int. Cl. G02F 1/1368 (2006.01); G02F 1/1362 (2006.01)
CPC G02F 1/1368 (2013.01) [G02F 1/136286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An array substrate, wherein the array substrate comprises a plurality of scanning lines and a plurality of data lines, a plurality of pixel units are enclosed by the plurality of scanning lines and the plurality of data lines, the pixel units comprise a thin film transistor region and pixel electrode regions;
the pixel units comprise a thin film transistor layer disposed in the thin film transistor region and a pixel electrode layer disposed in the pixel electrode regions; the pixel electrode layer comprises a pixel electrode, the thin film transistor layer comprises a thin film transistor, and the pixel electrode is electrically connected to the thin film transistor; and
wherein the pixel units further comprise a shielding member disposed in the thin film transistor region, in a first direction, an interval between the shielding member and the pixel electrode is a first threshold value, and the first direction is parallel to an extending direction of the data lines.