CPC G01R 31/396 (2019.01) [G01R 31/3648 (2013.01); H02J 7/0071 (2020.01); H03M 1/44 (2013.01)] | 15 Claims |
1. An apparatus comprising:
a plurality of analog front ends (AFEs);
a plurality of analog-to-digital converters (ADCs), wherein each one of the plurality of ADCs is coupled to one corresponding AFE of the plurality of AFEs, and wherein the plurality of ADCs produce a plurality of digital signals;
a plurality of digital channel registers, wherein each one of the plurality of digital channel registers is coupled to one corresponding ADC of the plurality of AFEs; and
a processor coupled to at least one ADC and configured to adjust the plurality of digital signals based on a plurality of common mode voltage values and a plurality of common mode to differential gain values associated with the plurality of AFEs.
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