US 12,032,021 B2
Method of testing a stacked integrated circuit device
Stephen Felix, Bristol (GB); and Phillip Horsfield, Bristol (GB)
Assigned to Graphcore Limited, Bristol (GB)
Filed by Graphcore Limited, Bristol (GB)
Filed on Sep. 22, 2022, as Appl. No. 17/934,250.
Claims priority of application No. 2114437 (GB), filed on Oct. 8, 2021.
Prior Publication US 2023/0114044 A1, Apr. 13, 2023
Int. Cl. G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01)
CPC G01R 31/318555 (2013.01) [G01R 31/31724 (2013.01); G01R 31/3177 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method for testing a stacked integrated circuit device comprising a first die and a second die, the method comprising:
sending first testing control signals to first testing apparatus on the first die from testing logic of the first die;
in response to the first testing control signals, the first testing apparatus running a first one or more tests for testing functional logic or memory of the first die;
sending second testing control signals from the testing logic of the first die to the second die by first through silicon vias formed in a substrate of the first die; and
in dependence upon the second testing control signals from the first die, running a second one or more tests for testing the stacked integrated circuit device.