US 12,032,019 B2
Clock conversion device, test system having the same, and method of operating test system
Yongjeong Kim, Cheonan-si (KR); Jongjin An, Asan-si (KR); Seonggwon Jang, Asan-si (KR); Pilho Lee, Asan-si (KR); and Inhoon Jang, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 24, 2022, as Appl. No. 17/582,385.
Claims priority of application No. 10-2021-0081050 (KR), filed on Jun. 22, 2021.
Prior Publication US 2022/0404417 A1, Dec. 22, 2022
Int. Cl. G01R 31/3177 (2006.01); G01R 31/28 (2006.01); G01R 31/30 (2006.01); G01R 31/317 (2006.01); G01R 31/319 (2006.01); H01L 21/66 (2006.01); H03K 3/017 (2006.01); H03K 19/21 (2006.01); H03L 7/099 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/2834 (2013.01); G01R 31/3004 (2013.01); G01R 31/31727 (2013.01); G01R 31/31924 (2013.01); H03K 3/017 (2013.01); H03K 19/21 (2013.01); H03L 7/099 (2013.01); H01L 22/34 (2013.01); H01L 2924/00 (2013.01); H01L 2924/0002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A clock conversion device comprising:
a first clock generator configured to receive a first input clock signal from test logic and generate a first clock signal of which a frequency is multiplied and a phase is locked;
a clock conversion circuit configured to receive the first clock signal and generate one or more second clock signals by converting at least one clock characteristic of the first clock signal; and
an output selector configured to output any one of the first clock signal and the one or more second clock signals as an output clock signal,
wherein the clock conversion device is configured to provide the output clock signal to a device under test (DUT).