CPC H10B 12/312 (2023.02) [G11C 11/4085 (2013.01); G11C 11/4097 (2013.01); H10B 12/50 (2023.02)] | 15 Claims |
1. A method for fabricating a memory device, comprising:
forming a plurality of active layers arranged vertically with respect to a substrate;
forming a vertically oriented active body that penetrates through the active layers to interconnect the active layers to each other;
forming a vertically oriented bit line that is spaced apart from one side of the active body and penetrates through the active layers;
forming a vertically oriented capacitor that is spaced apart from another side of the active body and penetrates through the active layers; and
forming a plurality of word lines that are laterally oriented adjacent to one side of each of the active layers.
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