US 11,700,723 B2
Semiconductor memory device
Seungjae Jung, Suwon-si (KR); Kwangho Park, Cheonan-si (KR); and Jaehoon Kim, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 5, 2021, as Appl. No. 17/193,739.
Claims priority of application No. 10-2020-0098193 (KR), filed on Aug. 5, 2020.
Prior Publication US 2022/0045064 A1, Feb. 10, 2022
Int. Cl. H01L 27/06 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/30 (2023.02) [H10B 12/03 (2023.02); H10B 12/05 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first semiconductor pattern, and a second semiconductor pattern separated from the first semiconductor pattern in a vertical direction;
a first bit line electrically connected to a first source/drain region of the first semiconductor pattern, and a second bit line electrically connected to a first source/drain region of the second semiconductor pattern;
a word line structure in contact with the first semiconductor pattern and the second semiconductor pattern; and
a first data storage element electrically connected to a second source/drain region of the first semiconductor pattern, and a second data storage element electrically connected to a second source/drain region of the second semiconductor pattern,
wherein the first semiconductor pattern and the second semiconductor pattern are monocrystalline, and
wherein a crystal orientation of the first semiconductor pattern is different from a crystal orientation of the second semiconductor pattern,
wherein at least one of the first semiconductor pattern and the second semiconductor pattern includes a lattice defect extending to a bottom surface or top surface of the at least one of the first semiconductor pattern and the second semiconductor pattern.