US 11,700,634 B2
Packet switch and method of setting time slot
Norikazu Hikimochi, Kanazawa (JP); Kazuto Nishimura, Yokohama (JP); and Yoshikazu Sabetto, Fukuoka (JP)
Assigned to FUJITSU LIMITED, Kawasaki (JP)
Filed by FUJITSU LIMITED, Kawasaki (JP)
Filed on May 3, 2021, as Appl. No. 17/246,729.
Claims priority of application No. 2020-123039 (JP), filed on Jul. 17, 2020.
Prior Publication US 2022/0022200 A1, Jan. 20, 2022
Int. Cl. H04W 72/56 (2023.01); H04W 72/0446 (2023.01); H04W 72/52 (2023.01)
CPC H04W 72/56 (2023.01) [H04W 72/0446 (2013.01); H04W 72/52 (2023.01)] 8 Claims
OG exemplary drawing
 
1. A packet switch comprising:
a memory; and
a processor coupled to the memory and configured to:
learn a pattern of a high-priority packet having a cyclicity;
monitor a burst end point of the high-priority packet, based on a result of the learning;
detect a shift of a time slot of the burst end point when a traffic flow rate of the high-priority packet changes; and
determine the time slot to close transmission of a non-priority packet, based on the shift of the time slot.