CPC H04W 72/56 (2023.01) [H04W 72/0446 (2013.01); H04W 72/52 (2023.01)] | 8 Claims |
1. A packet switch comprising:
a memory; and
a processor coupled to the memory and configured to:
learn a pattern of a high-priority packet having a cyclicity;
monitor a burst end point of the high-priority packet, based on a result of the learning;
detect a shift of a time slot of the burst end point when a traffic flow rate of the high-priority packet changes; and
determine the time slot to close transmission of a non-priority packet, based on the shift of the time slot.
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