US 11,700,465 B2
Solid-state imaging element, imaging device, and solid-state imaging element control method
Naoto Nagaki, Kanagawa (JP); and Takao Konishi, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/756,466
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Dec. 1, 2020, PCT No. PCT/JP2020/044592
§ 371(c)(1), (2) Date May 25, 2022,
PCT Pub. No. WO2021/112059, PCT Pub. Date Jun. 10, 2021.
Claims priority of application No. 2019-220811 (JP), filed on Dec. 6, 2019.
Prior Publication US 2023/0007194 A1, Jan. 5, 2023
Int. Cl. H04N 25/671 (2023.01); H04N 25/50 (2023.01); H04N 25/77 (2023.01); H04N 17/00 (2006.01); H04N 25/677 (2023.01); H03M 1/10 (2006.01); H03M 1/12 (2006.01); H03M 1/08 (2006.01)
CPC H04N 25/671 (2023.01) [H04N 17/002 (2013.01); H04N 25/50 (2023.01); H04N 25/77 (2023.01)] 10 Claims
OG exemplary drawing
 
1. A solid-state imaging element, comprising:
a test signal source configured to generate a test signal of a predetermined level;
an analog-to-digital converter configured to one of increase or decrease an analog signal according to an analog gain selected from among a plurality of analog gains, and convert the one of increased or decreased analog signal to a digital signal;
an input switching section configured to input, as the analog signal, either the test signal or a pixel signal to the analog-to-digital converter;
a correction value calculation section configured to obtain, based on the test signal and the digital signal, a correction value for correcting an error in the selected analog gain, and output the correction value; and
a correction section configured to correct the digital signal according to the outputted correction value.