CPC H04L 63/166 (2013.01) [H04L 63/0435 (2013.01); H04L 63/0442 (2013.01); H04L 63/061 (2013.01); H04L 63/062 (2013.01); H04L 63/20 (2013.01); H04W 12/04 (2013.01)] | 20 Claims |
1. A method for securely accessing data, the method comprising:
storing a first set of translation data at a first data storage device separate from a system memory that is physically accessible only by a first processor of a multi-processor system, the first set of translation data associated with a first connection, wherein the first set of translation data maps a first virtual address to a first physical memory location that is only accessible to the first processor while servicing the first connection;
storing a second set of translation data in a second data storage device separate from the system memory that is physically accessible only by a second processor of the multi-processor system, the second set of translation data associated with a second connection, wherein the second set of translation data maps a second virtual address to a second physical memory location that is only accessible to the second processor while servicing the second connection;
accessing the first physical memory location that stores data associated with the first connection by the first processor, the first physical memory location accessed after the first processor translates the first virtual address to a first physical memory address using the first data storage device, wherein data stored at the first physical memory address is secured based on the first set of translation data being accessible only by the first processor;
accessing the second physical memory location that stores data associated with the second connection by the second processor, the second physical memory location accessed after the second processor translates the second virtual address to a second physical memory address using the second data storage device, wherein data stored at the second physical memory address is secured based on the second set of translation data being accessible only by the second processor;
securely communicating with a first destination associated with the first connection after accessing the first physical memory address; and
securely communicating with to a second destination associated with the second connection after accessing the second physical memory location.
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