CPC H04L 47/6255 (2013.01) [H04L 49/901 (2013.01); H04L 67/568 (2022.05)] | 23 Claims |
1. An apparatus comprising:
a memory;
circuitry to provide a path for tag delivery;
a buffer to receive a tag from the circuitry to provide a path for tag delivery; and
second circuitry to:
determine a packet to egress using an available tag from one of: the memory or the buffer, wherein:
the circuitry is to provide a lower latency tag access than that of the memory,
the circuitry to provide tag delivery independent of access to the memory, and
the buffer is associated with an egress port.
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