US 11,700,209 B2
Multi-path packet descriptor delivery scheme
Robert Southworth, Chatsworth, CA (US); Karl S. Papadantonakis, Agoura Hills, CA (US); Mika Nystroem, Pasadena, CA (US); Arvind Srinivasan, San Jose, CA (US); David Arditti Ilitzky, Zapopan (MX); and Jonathan Dama, Encino, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 26, 2019, as Appl. No. 16/727,543.
Claims priority of provisional application 62/908,490, filed on Sep. 30, 2019.
Prior Publication US 2020/0136986 A1, Apr. 30, 2020
Int. Cl. H04L 47/625 (2022.01); H04L 49/901 (2022.01); H04L 67/568 (2022.01)
CPC H04L 47/6255 (2013.01) [H04L 49/901 (2013.01); H04L 67/568 (2022.05)] 23 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory;
circuitry to provide a path for tag delivery;
a buffer to receive a tag from the circuitry to provide a path for tag delivery; and
second circuitry to:
determine a packet to egress using an available tag from one of: the memory or the buffer, wherein:
the circuitry is to provide a lower latency tag access than that of the memory,
the circuitry to provide tag delivery independent of access to the memory, and
the buffer is associated with an egress port.