US 11,700,009 B2
Analog to digital converter with current mode stage
Martin Kinyua, Cedar Park, TX (US); and Eric Soenen, Austin, TX (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 11, 2022, as Appl. No. 17/717,519.
Application 17/717,519 is a continuation of application No. 17/120,438, filed on Dec. 14, 2020, granted, now 11,303,292.
Application 17/120,438 is a continuation of application No. 16/359,495, filed on Mar. 20, 2019, granted, now 10,868,557, issued on Dec. 15, 2020.
Claims priority of provisional application 62/650,536, filed on Mar. 30, 2018.
Prior Publication US 2022/0239307 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 1/38 (2006.01); H03M 1/14 (2006.01); H03M 1/06 (2006.01); H03M 1/16 (2006.01)
CPC H03M 1/145 (2013.01) [H03M 1/0612 (2013.01); H03M 1/164 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An analog-to-digital converter (ADC), comprising:
an input terminal configured to receive an analog input voltage;
a first sub-ADC stage coupled to the input terminal and configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to the analog input voltage in response to a second phase clock signal;
a current mode digital-to-analog converter (DAC) stage including
a transconductance amplifier (Gm) connected to the input terminal, the transconductance amplifier having a first plurality of transconductance amplifier cells, the transconductance amplifier configured to sample the analog input voltage in response to the first phase clock signal and convert the analog input voltage to a first current signal,
a current mode DAC connected to a sub-ADC output terminal of the first sub-ADC stage, the current mode DAC having a second plurality of current mode DAC unit cells and configured to convert the first digital value to a second current signal,
the current mode DAC stage configured to determine a residue current signal representing a difference between the first current signal and the second current signal, and convert the residue current signal to an analog residual voltage signal;
a second ADC stage coupled to the current mode DAC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value;
an alignment and digital error correction stage configured to combine the first and the second digital values into a digital output voltage; and
an output terminal coupled to the alignment and error correction stage configured to output the digital output voltage.