CPC H03L 7/0891 (2013.01) [H03L 7/101 (2013.01)] | 20 Claims |
1. A phase locked loop (PLL) circuit, comprising:
a load circuit that generates an output signal in response to a driving voltage;
a frequency calibration circuit that generates a calibration signal in response to an output frequency of the output signal and a target frequency; and
a regulator that generates the driving voltage in response to the calibration signal.
|