CPC H03K 19/17736 (2013.01) [H03K 19/17796 (2013.01); H04L 41/5019 (2013.01); H04L 41/5003 (2013.01)] | 20 Claims |
1. An integrated circuit comprising:
a first programmable logic circuit;
a second programmable logic circuit; and
a network-on-chip (NoC) between the first programmable logic circuit and the second programmable logic circuit, wherein the NoC has a configurable data width, and wherein the NoC comprises:
a plurality of data paths that collectively have the configurable data width; and
a plurality of packet switches interconnected to each other through respective paths of the plurality of data paths, wherein a first packet switch of the plurality of packet switches:
receives a first packet from the first programmable logic circuit, wherein the first packet comprises a destination identifier;
performs a first lookup operation in a table based on the destination identifier; and
transmits, using one of the data paths of the plurality of data paths, the first packet to a second packet switch of the plurality of packet switches based at least in part on a result of the first lookup operation.
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