US 11,699,995 B2
Multiplexer with highly linear analog switch
Vaibhav Garg, Jagadhri (IN); Abhishek Jain, Delhi (IN); and Anand Kumar, Noida (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Nov. 19, 2021, as Appl. No. 17/531,654.
Claims priority of provisional application 63/120,552, filed on Dec. 2, 2020.
Prior Publication US 2022/0173736 A1, Jun. 2, 2022
Int. Cl. H03K 17/693 (2006.01); H03K 17/687 (2006.01); H03K 19/017 (2006.01)
CPC H03K 17/6872 (2013.01) [H03K 17/6874 (2013.01); H03K 17/693 (2013.01); H03K 19/01735 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A multiplexer, comprising:
an input terminal;
an output terminal;
a main switch coupled between the input terminal and the output terminal and configured to pass a signal between the input terminal and the output terminal, wherein the main switch is a transistor including:
a source terminal coupled to the input terminal;
a drain terminal coupled to the output terminal; and
a gate terminal;
a first boot strap circuit including a first bootstrap capacitor and configured to couple the first bootstrap capacitor to the main switch during a first phase and to decouple the first bootstrap capacitor from the main switch during a second phase; and
a second boot strap circuit including a second bootstrap capacitor and configured to couple the second bootstrap capacitor to the main switch during the second phase and to decouple the second bootstrap capacitor from the main switch during the first phase, wherein during the first phase the first bootstrap capacitor is coupled between the source and gate terminals of the transistor and the second bootstrap capacitor is decoupled from the source and gate terminals of the transistor.