US 11,699,764 B2
Semiconductor device and method of manufacturing the same
Kazumi Takagiwa, Matsumoto (JP); and Hitoshi Sumida, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed by FUJI ELECTRIC CO., LTD., Kawasaki (JP)
Filed on Jan. 31, 2022, as Appl. No. 17/589,171.
Claims priority of application No. 2021-36540 (JP), filed on Mar. 8, 2021.
Prior Publication US 2022/0285563 A1, Sep. 8, 2022
Int. Cl. H01L 29/808 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/808 (2013.01) [H01L 29/4175 (2013.01); H01L 29/42312 (2013.01); H01L 29/66681 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising: a semiconductor layer of a first conductivity-type; a well region of a second conductivity-type provided at an upper part of the semiconductor layer; a base region of the second conductivity-type provided at an upper part of the well region and having an impurity concentration higher than an impurity concentration of the well region; a carrier supply region of the first conductivity-type provided at an upper part of the base region; a drift region of the first conductivity-type provided at the upper part of the well region separately from the base region; a carrier reception region of the first conductivity-type provided at an upper part of the drift region and having an impurity concentration higher than an impurity concentration of the drift region; a gate electrode provided on a top surface of the well region interposed between the base region and the drift region via a gate insulating film; and a punch-through prevention region of the second conductivity-type provided at the upper part of the well region and having an impurity concentration higher than the impurity concentration of the well region and different from the impurity concentration of the base region.