US 11,699,756 B2
Source/drain diffusion barrier for germanium nMOS transistors
Glenn A. Glass, Portland, OR (US); Anand S. Murthy, Portland, OR (US); Karthik Jambunathan, Hillsboro, OR (US); Cory C. Bomberger, Portland, OR (US); Tahir Ghani, Portland, OR (US); Jack T. Kavalieros, Portland, OR (US); Benjamin Chu-Kung, Boise, ID (US); Seung Hoon Sung, Portland, OR (US); and Siddharth Chouksey, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 2, 2021, as Appl. No. 17/541,199.
Application 17/541,199 is a continuation of application No. 16/641,022, granted, now 11,222,977, previously published as PCT/US2017/053474, filed on Sep. 26, 2017.
Prior Publication US 2022/0093797 A1, Mar. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 29/167 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/7846 (2013.01) [H01L 29/167 (2013.01); H01L 29/41791 (2013.01); H01L 29/42364 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a body of semiconductor material, the semiconductor material comprising germanium;
a gate structure on the body, the gate structure including a gate dielectric and a gate electrode, and the gate structure having a gate-all-around (GAA) configuration on the body of semiconductor material;
a source region and a drain region both adjacent to the body such that the body is between the source and drain regions, at least one of the source region and the drain region including n-type impurity;
a shallow trench isolation (STI) region adjacent the at least one of the source region and the drain region; and
a layer of insulation material between the at least one of the source region and the drain region and the STI region, wherein the layer of insulation material is distinct from the STI region, and wherein the layer of insulation material comprises silicon, oxygen and carbon.