US 11,699,755 B2
Stress incorporation in semiconductor devices
Ashish Pal, San Ramon, CA (US); Mehdi Saremi, Santa Clara, CA (US); El Mehdi Bazizi, San Jose, CA (US); and Benjamin Colombeau, San Jose, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Aug. 24, 2020, as Appl. No. 17/546.
Prior Publication US 2022/0059698 A1, Feb. 24, 2022
Int. Cl. H01L 29/78 (2006.01)
CPC H01L 29/7842 (2013.01) 14 Claims
OG exemplary drawing
 
1. A semiconductor processing method comprising:
depositing a stressed material on an adjacent layer, wherein the adjacent layer is disposed between and in contact with each of the stressed material and a substrate comprising doped source and drain regions, and wherein the adjacent layer is characterized by an increased stress level after the deposition of the stressed material, wherein the stressed material has a tensile stress greater than or about 4 GPa;
heating the stressed material and the adjacent layer; and
removing the stressed material from the adjacent layer, wherein the adjacent layer retains at least a portion of increased stress after the removal of the stressed material.