CPC H01L 29/42372 (2013.01) [H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H10B 41/41 (2023.02); H10B 43/40 (2023.02)] | 14 Claims |
1. A method for forming a memory device, comprising:
forming a bottom-select-gate (BSG) structure on a substrate;
forming cut slits vertically through the BSG structure on the substrate;
forming a cell-layers structure on the BSG structure; and
forming gate-line slits that are vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish a plurality of finger regions, wherein:
the gate-line slits include a first gate-line slit between first and second finger regions of the plurality of finger regions, the first gate-line slit including gate-line sub-slits, and
the cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit of the first gate-line slit to define a BSG in a first portion of the second finger region, wherein:
the BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit of the first gate-line slit.
|