US 11,699,693 B2
Memory device
Jooyong Park, Hwaseong-si (KR); Chanho Kim, Seoul (KR); and Daeseok Byeon, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-do (KR)
Filed on Dec. 8, 2021, as Appl. No. 17/545,522.
Application 17/545,522 is a continuation of application No. 16/942,854, filed on Jul. 30, 2020, granted, now 11,227,860.
Application 16/942,854 is a continuation in part of application No. 16/816,476, filed on Mar. 12, 2020, granted, now 11,120,843, issued on Sep. 14, 2021.
Claims priority of application No. 10-2019-0108359 (KR), filed on Sep. 2, 2019.
Prior Publication US 2022/0102335 A1, Mar. 31, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/18 (2023.01); H01L 25/065 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first chip configured to include a memory cell array disposed on a first substrate, and a plurality of first metal pads on a first uppermost metal layer of the first chip; and
a second chip configured to include peripheral circuits disposed on a second substrate, and a plurality of second metal pads on a second uppermost metal layer of the second chip, the peripheral circuits operating the memory cell array,
wherein at least one of the plurality of first metal pads of the first chip and at least one of the plurality of second metal pads of the second chip are connected in a first area, the at least one of the plurality of first metal pads being connected to the memory cell array and the at least one of the plurality of second metal pads being connected to the peripheral circuits, and
wherein a further at least one of the plurality of first metal pads of the first chip and a further at least one of the plurality of second metal pads of the second chip are connected in a second area, the further at least one of the plurality of first metal pads being not connected to the memory cell array and the further at least one of the plurality of second metal pads being connected to the peripheral circuits, and
wherein the further at least one of the plurality of second metal pads forms a power routing wire used for supplying power to the peripheral circuits of the second chip.