CPC H01L 25/0657 (2013.01) [G11C 11/407 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a stack of semiconductor chips, the stack of semiconductor chips comprising a logic chip that is vertically stacked with a memory stack, wherein, the logic chip comprises at least one of a GPU and CPU, the stack of semiconductor chips comprising a first semiconductor chip at a first end of the stack of semiconductor chips and a second semiconductor chip at a second end of the stack of semiconductor chips; and
a semiconductor chip substrate, the stack of semiconductor chips mounted on the semiconductor chip substrate at a first face of the first semiconductor chip, at least one other logic chip mounted on the semiconductor chip substrate, the at least one other logic chip not vertically stacked with the stack of semiconductor chips, the semiconductor chip substrate comprising wiring to interconnect the stack of semiconductor chips to the at least one other logic chip, wherein, electrical power is to be received at a second face of the second semiconductor chip that faces a direction opposite that of the first face of the first semiconductor chip.
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