US 11,699,681 B2
Multi-chip module having a stacked logic chip and memory stack
Abhishek Sharma, Hillsboro, OR (US); Hui Jae Yoo, Hillsboro, OR (US); Van H. Le, Beaverton, OR (US); Huseyin Ekin Sumbul, Portland, OR (US); Phil Knag, Hillsboro, OR (US); Gregory K. Chen, Portland, OR (US); and Ram Krishnamurthy, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 26, 2019, as Appl. No. 16/727,779.
Prior Publication US 2020/0135700 A1, Apr. 30, 2020
Int. Cl. H01L 25/065 (2023.01); G11C 11/407 (2006.01)
CPC H01L 25/0657 (2013.01) [G11C 11/407 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a stack of semiconductor chips, the stack of semiconductor chips comprising a logic chip that is vertically stacked with a memory stack, wherein, the logic chip comprises at least one of a GPU and CPU, the stack of semiconductor chips comprising a first semiconductor chip at a first end of the stack of semiconductor chips and a second semiconductor chip at a second end of the stack of semiconductor chips; and
a semiconductor chip substrate, the stack of semiconductor chips mounted on the semiconductor chip substrate at a first face of the first semiconductor chip, at least one other logic chip mounted on the semiconductor chip substrate, the at least one other logic chip not vertically stacked with the stack of semiconductor chips, the semiconductor chip substrate comprising wiring to interconnect the stack of semiconductor chips to the at least one other logic chip, wherein, electrical power is to be received at a second face of the second semiconductor chip that faces a direction opposite that of the first face of the first semiconductor chip.