US 11,699,650 B2
Integrated circuit structure with capacitor electrodes in different ILD layers, and related methods
Alamgir M. Arif, Saratoga Springs, NY (US); Sunil K. Singh, Mechanicville, NY (US); Dewei Xu, Clifton Park, NY (US); Seung-Yeop Kook, Mechanicville, NY (US); and Roderick A. Augur, Saratoga Springs, NY (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GLOBALFOUNDRIES U.S. Inc., Santa Clara, CA (US)
Filed on Jan. 18, 2021, as Appl. No. 17/151,346.
Prior Publication US 2022/0230955 A1, Jul. 21, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 49/02 (2006.01)
CPC H01L 23/5223 (2013.01) [H01L 23/5226 (2013.01); H01L 28/60 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) structure, comprising:
a first inter-level dielectric (ILD) layer having a top surface;
a barrier film on the top surface of the first ILD layer;
a first vertical electrode within the first ILD layer;
a capacitor dielectric film on a top surface of the first vertical electrode and at least partially within the barrier layer;
a second ILD layer over the first ILD layer; and
a second vertical electrode within the second ILD layer and on the capacitor dielectric film, wherein the capacitor dielectric film is vertically between the first vertical electrode and the second vertical electrode,
wherein the capacitor dielectric film includes:
a first portion vertically between the first vertical electrode and the second vertical electrode; and
a second portion above the first portion, and horizontally between an outer circumference of the second vertical electrode and the second ILD layer.