US 11,699,644 B2
Organic mold interconnects in shielded interconnects frames for integrated-circuit packages
Jiun Hann Sir, Gelugor (MY); Eng Huat Goh, Penang (MY); and Poh Boon Khoo, Perai (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 17, 2021, as Appl. No. 17/529,093.
Application 17/529,093 is a continuation of application No. 16/912,653, filed on Jun. 25, 2020, granted, now 11,205,613.
Claims priority of application No. PI2019005652 (MY), filed on Sep. 26, 2019.
Prior Publication US 2022/0077047 A1, Mar. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/552 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01)
CPC H01L 23/49827 (2013.01) [H01L 21/486 (2013.01); H01L 23/552 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An integrated-circuit package assembly, comprising:
an integrated-circuit (IC) package substrate, including a die side and a land side;
a plurality of interconnects located at a periphery of the package substrate, including:
an input/output interconnect that extends at least the height of the IC package land side to a redistribution layer near the IC package die side, wherein the input/output interconnect is shielded by a ground (Vss) annulus;
a power interconnect that extends at least the height of the IC package land side to the redistribution layer near the IC package die side, wherein the power interconnect is shielded by a ground (Vss) annulus;
wherein the redistribution layer is coupled to each of the IC package substrate, the input/output interconnect and the power interconnect.