US 11,699,643 B2
Fan-out semiconductor package
Ik Jun Choi, Suwon-si (KR); Jae Ean Lee, Suwon-si (KR); Kwang Ok Jeong, Suwon-si (KR); Young Gwan Ko, Suwon-si (KR); and Jung Soo Byun, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 29, 2021, as Appl. No. 17/162,015.
Application 17/162,015 is a continuation of application No. 15/935,526, filed on Mar. 26, 2018, granted, now 10,916,495.
Claims priority of application No. 10-2017-0139983 (KR), filed on Oct. 26, 2017.
Prior Publication US 2021/0151370 A1, May 20, 2021
Int. Cl. H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/528 (2006.01); H01L 21/48 (2006.01); H01L 23/522 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49822 (2013.01) [H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/49827 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 24/18 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/18 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor package, the method comprising:
disposing a semiconductor chip having contact pads, and a connection structure around the semiconductor chip on a supporting substrate, with the contact pads facing the supporting substrate;
forming an encapsulant encapsulating the semiconductor chip and the connection structure on the supporting substrate;
embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole;
forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure; and
forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.
 
8. A method for manufacturing a semiconductor package, the method comprising:
preparing a package structure comprising a connection member including a first redistribution layer, a semiconductor chip having disposed on the connection member, a connection structure disposed around the semiconductor chip on the connection member, and an encapsulant encapsulating the semiconductor chip and the connection structure on the connection member, the first redistribution layer electrically connecting the semiconductor chip and a lower surface of the connection structure:
embedding a wiring pattern having a connection portion in the encapsulant, the connection portion having a connection hole;
forming a through hole penetrating the encapsulant in the connection hole, the through hole exposing a portion of an upper surface of the connection structure; and
forming a conductive via in the through hole, the conductive via connecting the wiring pattern to the connection structure.