US 11,699,613 B2
Semiconductor devices and methods of fabricating the same
Sunguk Jang, Hwaseong-si (KR); Seokhoon Kim, Suwon-si (KR); Seung Hun Lee, Hwaseong-si (KR); Yang Xu, Suwon-si (KR); Jeongho Yoo, Jeongnam-si (KR); Jongryeol Yoo, Osan-si (KR); and Youngdae Cho, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 30, 2020, as Appl. No. 17/137,485.
Application 17/137,485 is a continuation of application No. 15/869,718, filed on Jan. 12, 2018, granted, now 10,903,108.
Claims priority of application No. 10-2017-0148218 (KR), filed on Nov. 8, 2017.
Prior Publication US 2021/0143049 A1, May 13, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/76 (2006.01); H01L 21/762 (2006.01); H01L 21/225 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/762 (2013.01) [H01L 21/02164 (2013.01); H01L 21/02181 (2013.01); H01L 21/02225 (2013.01); H01L 21/2253 (2013.01); H01L 21/76229 (2013.01); H01L 21/76232 (2013.01); H01L 29/165 (2013.01); H01L 29/42316 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit device, the method comprising:
sequentially forming a first epitaxial layer and a second epitaxial layer on a substrate, wherein the first epitaxial layer comprises a material different from the second epitaxial layer, and a thickness of the first epitaxial layer is from about 10 Å to about 100 Å;
implanting dopants into the second epitaxial layer to form a preliminary impurity region in the second epitaxial layer;
heating the substrate to convert the preliminary impurity region into an impurity region;
forming a third epitaxial layer on the substrate after heating the substrate;
forming a first trench and a second trench in the third epitaxial layer and the impurity region to define an active in between the first trench and the second trench;
forming a first isolation layer and a second isolation layer in the first trench and the second trench, respectively, wherein the active fin protrudes beyond upper surfaces of the first and second isolation layers such that the first and second isolation layers expose opposing sides of the active fin;
forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin; and
forming a gate electrode traversing the active fin.