US 11,699,502 B2
Simulating memory cell sensing for testing sensing circuitry
Iris Lu, Fremont, CA (US); Yan Li, Milpitas, CA (US); and Ohwon Kwon, Pleasanton, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Dec. 14, 2021, as Appl. No. 17/550,352.
Prior Publication US 2023/0187014 A1, Jun. 15, 2023
Int. Cl. G01R 31/3181 (2006.01); G11C 29/16 (2006.01); G11C 7/06 (2006.01); G11C 29/54 (2006.01); H10B 80/00 (2023.01); G01R 31/3177 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC G11C 29/54 (2013.01) [G01R 31/3181 (2013.01); G11C 7/065 (2013.01); G11C 7/067 (2013.01); G11C 29/16 (2013.01); H10B 80/00 (2023.02); G01R 31/3177 (2013.01); H01L 25/065 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a semiconductor die comprising a plurality of sense blocks and a control circuit in communication with the plurality of sense blocks, the sense blocks configured to be connected to a memory structure having non-volatile memory cells, wherein the control circuit is configured to:
control the plurality of sense blocks to simulate sensing of non-volatile memory cells in the memory structure when the sense blocks are not connected to the memory structure; and
verify correct operation of the semiconductor die based on the simulated sensing.