US 11,699,497 B2
Shift register, semiconductor device, display device, and electronic device
Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on May 3, 2021, as Appl. No. 17/246,842.
Application 17/246,842 is a continuation of application No. 16/424,813, filed on May 29, 2019, granted, now 11,011,244.
Application 16/424,813 is a continuation of application No. 15/584,117, filed on May 2, 2017, granted, now 10,311,960, issued on Jun. 4, 2019.
Application 15/584,117 is a continuation of application No. 14/800,765, filed on Jul. 16, 2015, granted, now 9,646,714, issued on May 9, 2017.
Application 14/800,765 is a continuation of application No. 11/539,429, filed on Oct. 6, 2006, granted, now 9,153,341, issued on Oct. 6, 2015.
Claims priority of application No. 2005-303771 (JP), filed on Oct. 18, 2005.
Prior Publication US 2021/0272643 A1, Sep. 2, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 19/18 (2006.01); G09G 3/36 (2006.01); G09G 3/3266 (2016.01)
CPC G11C 19/184 (2013.01) [G09G 3/3648 (2013.01); G09G 3/3677 (2013.01); G09G 3/3266 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/0289 (2013.01); G09G 2320/02 (2013.01); G09G 2320/043 (2013.01); G09G 2330/021 (2013.01); G09G 2330/023 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor; and
a fourth transistor,
wherein one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and an output terminal are electrically connected to one another,
wherein a gate of the first transistor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor are electrically connected to one another,
wherein a gate of the second transistor and a gate of the third transistor are electrically connected to one another,
wherein a gate signal line is electrically connected to the output terminal,
wherein a power source line is electrically connected to the other of the source and the drain of the second transistor, and the other of the source and the drain of the third transistor,
wherein a clock signal line is electrically connected to the other of the source and the drain of the first transistor, and
wherein, in a top view, a first conductive layer, a second conductive layer, and a third conductive layer are arranged so that the first conductive layer functioning as the power source line is located between the second conductive layer functioning as the clock signal line and the third conductive layer functioning as the output terminal, and the second conductive layer functioning as the clock signal line is not located between the first conductive layer functioning as the power source line and the third conductive layer functioning as the output terminal.