US 11,699,494 B2
Peak and average ICC reduction by tier-based sensing during program verify operations of non-volatile memory structures
Xue Bai Pitner, Sunnyvale, CA (US); Yu-Chung Lien, San Jose, CA (US); Deepanshu Dutta, Fremont, CA (US); Huai-yuan Tseng, San Ramon, CA (US); and Ravi Kumar, Redwood City, CA (US)
Assigned to SanDisk Technologies LLC
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jun. 7, 2021, as Appl. No. 17/340,826.
Prior Publication US 2022/0392552 A1, Dec. 8, 2022
Int. Cl. G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 2216/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for programming a memory block of a non-volatile memory structure, comprising:
during a program verify operation:
selecting only a partial segment of memory cells of a memory block for bit scan mode;
applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells; and
initiating a bit scan mode of the selected memory cells.