| CPC G11C 16/32 (2013.01) [G06F 1/10 (2013.01); G06F 3/0604 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/06562 (2013.01)] | 18 Claims |
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1. A storage system, comprising:
a memory controller which provides a clock signal;
a buffer which receives the clock signal output from the memory controller and re-drives the clock signal, the buffer including a sampler which receives a data signal and a data strobe signal regarding the data signal, and which outputs a data stream; and
a nonvolatile memory, including:
a first duty cycle corrector, which receives the clock signal through the buffer and outputs a corrected clock signal by performing a first duty correction operation on the clock signal; and
a data strobe signal generator, which generates the data strobe signal based on the corrected clock signal and provides the data strobe signal to the buffer,
wherein the buffer receives the data strobe signal output from the nonvolatile memory, senses a duty ratio of the data strobe signal input to the sampler, and performs a second duty correction operation on the duty ratio of the input data strobe signal,
wherein
the nonvolatile memory further includes a first comparator which senses a duty ratio of the clock signal and a first logic which generates a first digital code regarding the duty ratio of the clock signal, and
the buffer further includes a second comparator which senses the duty ratio of the data strobe signal input to the sampler and a second logic which generates a second digital code regarding the duty ratio of the data strobe signal.
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