CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/20 (2013.01); G11C 16/24 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] | 22 Claims |
1. A method of programming a memory block comprising a plurality of stacks connected in series in a vertical direction by forming a plurality of cell strings between a plurality of bitlines and a source line, the method comprising:
determining, from among the plurality of stacks, a selected stack comprising memory cells to be programmed according to a program command, the selected stack being separated from an erased stack comprising non-programmed memory cells by a boundary portion comprising a plurality of intermediate switching transistors;
during a first boosting period, applying a turn-on voltage to gate electrodes of the plurality of intermediate switching transistors;
during the first boosting period, applying a first pass voltage to wordlines of the erased stack;
during a second boosting period after the first boosting period, applying a turn-off voltage to the gate electrodes of the plurality of intermediate switching transistors;
during the second boosting period, applying a second pass voltage to wordlines of the selected stack; and
during a program execution period after the second boosting period, applying a program voltage to a selected wordline of the selected stack.
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