CPC G11C 16/08 (2013.01) [G11C 11/1657 (2013.01); H10B 12/053 (2023.02); H10B 41/30 (2023.02)] | 20 Claims |
1. An integrated chip comprising:
a substrate;
a first source/drain region and a second source/drain region in the substrate;
an erase gate, a control gate, and a word line overlying the substrate, wherein the erase gate overlies the first source/drain region, wherein the word line borders the second source/drain region, and wherein the control gate is between and borders the erase gate and the word line; and
a trench isolation structure extending into the substrate, wherein the trench isolation structure is between the first and second source/drain regions, and is closer to the second source/drain region than the first source/drain region, along an axis.
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