US 11,699,481 B2
Semiconductor memory device including word line and bit line
Kee Teok Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jul. 11, 2022, as Appl. No. 17/862,081.
Application 17/862,081 is a continuation of application No. 17/150,854, filed on Jan. 15, 2021, granted, now 11,386,950.
Claims priority of application No. 10-2020-0099974 (KR), filed on Aug. 10, 2020.
Prior Publication US 2022/0343971 A1, Oct. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/12 (2006.01); G11C 11/4094 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4094 (2013.01) [G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); H10B 12/30 (2023.02); H10B 12/50 (2023.02); G11C 7/12 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first bit line and a second bit line which are arranged in parallel on a first plane;
a lower word line arranged to intersect the first and the second bit lines to form lower memory cells, the lower word line arranged in a second plane located below the first plane on which the first and second bit lines are arranged; and
an upper word line arranged to intersect the first and the second bit lines to form upper memory cells, the upper word line arranged in a third plane located above the first plane,
wherein the first bit line is spaced apart from the lower word line by a first distance at an intersection of the first bit line and the lower word line, and
wherein the first bit line is spaced apart from the upper word line by a second distance different from the first distance at an intersection of the first bit line and the upper word line.