US 11,699,480 B2
Semiconductor memory device with column path control circuit that controls column path for accessing a core circuit with multiple bank groups and column path control circuit therefor
Ji Eun Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jul. 26, 2021, as Appl. No. 17/443,412.
Claims priority of application No. 10-2021-0024602 (KR), filed on Feb. 24, 2021.
Prior Publication US 2022/0270666 A1, Aug. 25, 2022
Int. Cl. G11C 7/22 (2006.01); G11C 11/4094 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 8/12 (2006.01); G11C 8/18 (2006.01); H01L 25/065 (2023.01); G11C 7/12 (2006.01); G11C 7/06 (2006.01)
CPC G11C 11/4094 (2013.01) [G11C 8/12 (2013.01); G11C 8/18 (2013.01); G11C 11/408 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 7/06 (2013.01); G11C 7/12 (2013.01); H01L 25/0657 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a core circuit including a plurality of memory cell arrays electrically connected between a plurality of row lines and a plurality of column lines; and
a column path control circuit configured to generate a preliminary column pulse from a command signal irrelevant to a column address signal, to generate a main column pulse in response to an enable time point of the column address signal and an enable time point of the preliminary column pulse, and to enable an access target column line among the plurality of column lines.