CPC G11C 11/4091 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 11/4099 (2013.01)] | 22 Claims |
1. A nonvolatile memory apparatus comprising:
a control circuit configured to apply a read voltage across a target memory cell by applying a first read boundary voltage to a selected global bit line and by applying a second read boundary voltage to a selected global word line;
a sense amplifier configured to generate an output signal by comparing voltage levels of the selected global word line and an unselected global word line that is not coupled to the target memory cell; and
a reference generator configured to change the voltage level of the unselected global word line by charging and discharging a capacitor that is coupled to the unselected global word line.
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