| CPC G11C 7/222 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1084 (2013.01)] | 20 Claims |
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1. A semiconductor memory device comprising:
a data clock buffer configured to generate first through fourth clock signals based on a data clock signal received from a memory controller;
a quadrature error correction circuit configured to receive the first through fourth clock signals, configured to perform a locking operation to generate a first corrected clock signal and a second corrected clock signal which have a phase difference of 90 degrees with respect to each other by adjusting at least one of a skew and a duty error of at least some of the first through fourth clock signals in a first operation mode based on an initialization command and configured to perform a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal in a second operation mode;
a clock generation circuit configured to generate an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal; and
a data input/output (I/O) buffer configured to generate a data signal by sampling data from a memory cell array based on the output clock signal and configured to transmit the data signal and the strobe signal to the memory controller.
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