US 11,699,467 B2
Data output buffer and semiconductor apparatus including the same
Kyu Dong Hwang, Icheon-si (KR); Bo Ram Kim, Icheon-si (KR); and Dae Han Kwon, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 28, 2021, as Appl. No. 17/361,018.
Claims priority of application No. 10-2021-0037586 (KR), filed on Mar. 23, 2021.
Prior Publication US 2022/0310135 A1, Sep. 29, 2022
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); H03K 19/00 (2006.01); H03K 19/017 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/1057 (2013.01); G11C 7/1096 (2013.01); H03K 19/0005 (2013.01); H03K 19/01742 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A data output buffer comprising:
a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code; and
a second driver configured to directly receive emphasis signals and the impedance calibration code, perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.