CPC G09G 3/3266 (2013.01) [G09G 3/3233 (2013.01); G09G 3/3275 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0238 (2013.01); G09G 2330/021 (2013.01)] | 17 Claims |
1. A scan driving circuit, comprising:
a first output terminal electrically connected to a first scan line;
a second output terminal electrically connected to a second scan line;
a first masking circuit electrically connecting the first output terminal and the second output terminal and outputting a first scan signal to the first output terminal in response to a first masking signal; and
a driving circuit outputting a first signal and a second scan signal to a first node and the second output terminal in response to clock signals and a carry signal, respectively wherein
the first masking circuit comprises a first transistor connected between the first output terminal and an input terminal receiving a first voltage, the first transistor including a gate electrode electrically connected to the first node.
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