| CPC G09G 3/3266 (2013.01) [G09G 3/3258 (2013.01); G09G 2310/0202 (2013.01)] | 10 Claims |
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1. A scan driver comprising:
a plurality of scan stages including an n-th scan stage and an (n+1)-th scan stage,
wherein:
odd-numbered scan stages among the plurality of scan stages are connected to a first sub-control line, and even-numbered scan stages among the plurality of scan stages are connected to a second sub-control line; and
the n-th scan stage comprises:
a first transistor having a gate electrode connected to a first Q node, one electrode connected to a first scan clock line, and another electrode connected to a first scan line;
a second transistor having a gate electrode and one electrode connected to a first scan carry line, and another electrode connected to the first Q node;
a fourth transistor having a gate electrode connected to a first control line, and one electrode connected to a first sensing carry line;
a fifth transistor having a gate electrode connected to another electrode of the fourth transistor and one electrode connected to a second control line;
a first capacitor having one electrode connected to the one electrode of the fifth transistor, and another electrode connected to the gate electrode of the fifth transistor; and
an eleventh transistor having a gate electrode connected to a first QB node, one electrode connected to the first Q node, and another electrode connected to a first power line.
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