US 11,699,017 B2
Die yield assessment based on pattern-failure rate simulation
Young Chang Kim, San Jose, CA (US); John L. Sturtevant, Portland, OR (US); Andrew Burbine, Rochester, NY (US); and Christopher Clifford, Alameda, CA (US)
Assigned to Siemens Industry Software Inc., Plano, TX (US)
Appl. No. 17/417,223
Filed by Siemens Industry Software Inc., Plano, TX (US)
PCT Filed Aug. 23, 2019, PCT No. PCT/US2019/047839
§ 371(c)(1), (2) Date Jun. 22, 2021,
PCT Pub. No. WO2020/162979, PCT Pub. Date Aug. 13, 2020.
Claims priority of provisional application 62/803,090, filed on Feb. 8, 2019.
Prior Publication US 2022/0075274 A1, Mar. 10, 2022
Int. Cl. G06F 30/30 (2020.01); G03F 7/20 (2006.01); G06F 30/398 (2020.01); G03F 7/00 (2006.01); G03F 1/36 (2012.01); G06F 119/18 (2020.01); G06F 119/22 (2020.01)
CPC G06F 30/398 (2020.01) [G03F 1/36 (2013.01); G03F 7/705 (2013.01); G03F 7/70441 (2013.01); G06F 2119/18 (2020.01); G06F 2119/22 (2020.01)] 17 Claims
OG exemplary drawing
 
1. A method comprising:
identifying, by a computing system, structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data;
determining, by the computing system, failure rates for the identified structures by:
generating the process windows for the identified structures based, at least in part, on a lithographic response of the mask layout data and a failure definition for the integrated circuit, and
integrating a distribution of manufacturing parameters during fabrication over the generated process windows for the identified structures;
determining, by the computing system, frequency of occurrences for the identified structures in the integrated circuit from the mask layout data; and
generating, by the computing system, a die yield metric for the integrated circuit based, at least in part, on the failure rates for the identified structures and frequency of occurrences for the identified structures in the integrated circuit.