CPC G06F 21/72 (2013.01) [H04L 9/06 (2013.01); H04L 9/0866 (2013.01); G06F 2221/2113 (2013.01)] | 12 Claims |
1. An integrated circuit, comprising:
a secure hardware environment configured to record a unique hardware key and comprising:
a first logic circuit configured to generate a unique derived key from said unique hardware key and at least one piece of information, wherein said at least one piece of information relates to one or more of an execution context and a use of a secret key;
a first encryption device configured to perform a symmetric encryption operation of said secret key using said unique derived key and to deliver an encrypted secret key outside the secure hardware environment which results from performance of the symmetric encryption operation;
a second encryption device configured to perform a further symmetric encryption operation of binary data using the secret key and to deliver encrypted binary data outside the secure hardware environment which results from performance of the further symmetric encryption operation
a first decryption device configured to perform a decryption operation of an encrypted secret key using said unique derived key and to deliver a secret key resulting from performance of the operation decryption; and
a second decryption device configured to perform a further decryption operation of encrypted binary data using the secret key delivered by the first decryption device and to deliver non-encrypted binary data resulting from performance of the further decryption operation.
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