US 11,698,876 B2
Quality of service control of logical devices for a memory sub-system
Horia C. Simionescu, Foster City, CA (US); Xiaodong Wang, Sunnyvale, CA (US); and Venkata Yaswanth Raparti, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 5, 2022, as Appl. No. 17/713,825.
Application 17/713,825 is a continuation of application No. 16/948,005, filed on Aug. 27, 2020, granted, now 11,321,257.
Claims priority of provisional application 62/956,034, filed on Dec. 31, 2019.
Prior Publication US 2022/0237133 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/32 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/32 (2013.01) [G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a plurality of requests to perform a plurality of input/output (TO) operations corresponding to a plurality of logical devices associated with a memory device;
assigning the plurality of requests to respective queues associated with the plurality of logic devices; and
iteratively processing the plurality of requests in view of respective numbers of operation credits associated with the plurality of logical devices, wherein the respective numbers of credits are based at least in part on respective sets of quality of service (QoS) parameters for the plurality of logical devices.