US 11,698,872 B2
Interfacing with systems, for processing data samples, and related systems, methods and apparatuses
Narendra Raj S V, Karnataka (IN); Priyank Gupta, Chandler, AZ (US); and Michael Simmons, Chandler, AZ (US)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on Dec. 1, 2021, as Appl. No. 17/457,185.
Application 17/457,185 is a division of application No. 16/258,171, filed on Jan. 25, 2019, granted, now 11,221,976.
Prior Publication US 2022/0092006 A1, Mar. 24, 2022
Int. Cl. G06F 13/16 (2006.01); G06F 3/06 (2006.01); G06F 5/06 (2006.01); G06F 13/28 (2006.01)
CPC G06F 13/1673 (2013.01) [G06F 3/061 (2013.01); G06F 3/0631 (2013.01); G06F 3/0647 (2013.01); G06F 3/0679 (2013.01); G06F 5/06 (2013.01); G06F 13/28 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
first interfaces to communicate at first data widths via first interconnects for operative coupling with data samples sources;
second interfaces to communicate at second data widths via second interconnects for operative coupling with data sinks,
wherein the second interfaces are different than the first interfaces, the second data widths are different than the first data widths, and the second interconnects are different than the first interconnects;
a bus interface to communicate at a third data width via a third interconnect for operative coupling with allocated memory regions utilized by a system to process data samples, the data samples sampled utilizing different sampling rates, according to processing frame durations,
wherein the third data widths are different than the first data widths and the second data widths, and the third interconnects are different than the first interconnects and the second interconnects; and
a buffer interface to communicate with the system to process data samples, the buffer interface comprising an uplink channel handler and a downlink channel handler,
wherein the uplink channel handler to receive data samples from the first interfaces at first data widths and provide the data samples to the bus interface at third data widths, and
wherein the downlink channel handler to receive processed data samples from the bus interface at third data widths and provide the processed data samples to the second interfaces at second data widths.