US 11,698,866 B2
Unified address translation for virtualization of input/output devices
Utkarsh Y. Kakaiya, Folsom, CA (US); Sanjay Kumar, Hillsboro, OR (US); Rajesh M. Sankaran, Portland, OR (US); Philip R. Lantz, Cornelius, OR (US); Ashok Raj, Portland, OR (US); and Kun Tian, Shanghai (CN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 16/651,786
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 29, 2017, PCT No. PCT/US2017/068938
§ 371(c)(1), (2) Date Mar. 27, 2020,
PCT Pub. No. WO2019/132976, PCT Pub. Date Jul. 4, 2019.
Prior Publication US 2021/0173790 A1, Jun. 10, 2021
Int. Cl. G06F 12/1009 (2016.01); G06F 9/455 (2018.01); G06F 12/06 (2006.01); G06F 12/1081 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 9/45558 (2013.01); G06F 12/063 (2013.01); G06F 12/1081 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45591 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus comprising:
first circuitry to use at least an identifier of a device to locate a context entry, the context entry to include at least one of a page-table pointer to a page-table translation structure and a process address space identifier (PASID); and
second circuitry to use at least the PASID to locate a PASID-entry, the PASID-entry to include at least one of a first-level page-table pointer to a first-level translation structure and a second-level page-table pointer to a second-level translation structure;
wherein the PASID is to be supplied by the device; and
wherein at least one of the apparatus and the context entry is to include one or more control fields to indicate which of the first-level page-table pointer and the second-level page-table pointer is to be used.