US 11,698,864 B2
Memory access collision management on a shared wordline
Abdelhakim Alhussien, San Jose, CA (US); Jiangang Wu, Milpitas, CA (US); Karl D. Schuh, Santa Cruz, CA (US); Qisong Lin, El Dorado Hills, CA (US); and Jung Sheng Hoei, Newark, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 25, 2022, as Appl. No. 17/824,676.
Application 17/824,676 is a continuation of application No. 16/817,384, filed on Mar. 12, 2020, granted, now 11,366,760.
Prior Publication US 2022/0283952 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 12/0882 (2016.01); G06F 12/02 (2006.01); G11C 11/408 (2006.01); G06F 9/30 (2018.01); G06F 9/4401 (2018.01)
CPC G06F 12/0882 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30098 (2013.01); G06F 9/4418 (2013.01); G06F 12/0246 (2013.01); G11C 11/4085 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
determining that a request to perform a read operation is directed to data stored on a same wordline and sub-block of the memory array on which a program operation is being performed;
responsive to determining that the request to perform the read operation is directed to data stored on the wordline and sub-block of the memory array on which the program operation is being performed, sending a suspend command to the memory device to cause the memory device to suspend the program operation; and
reading data corresponding to the read operation from a page cache of the memory device while the program operation is suspended.