US 11,698,862 B2
Three tiered hierarchical memory systems
Vijay S. Ramesh, Boise, ID (US); Anton Korzh, Santa Clara, CA (US); Richard C. Murphy, Boise, ID (US); and Scott Matthew Stephens, Covington, WA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 22, 2021, as Appl. No. 17/382,953.
Application 17/382,953 is a continuation of application No. 16/547,635, filed on Aug. 22, 2019, granted, now 11,074,182.
Prior Publication US 2021/0349822 A1, Nov. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/02 (2006.01); G06F 12/0811 (2016.01); G06F 3/06 (2006.01)
CPC G06F 12/0811 (2013.01) [G06F 12/0246 (2013.01); G06F 3/0656 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/305 (2013.01); G06F 2212/608 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first non-persistent memory; and
a second non-persistent memory configured to map an address associated with an input/output (I/O) device to an address in the first non-persistent memory subsequent to the apparatus receiving a request from the I/O device to access data stored in a persistent memory of the apparatus, wherein:
the address associated with the I/O device is contiguous with other addresses associated with the I/O device mapped by the second non-persistent memory; and
the address in the first non-persistent memory to which the address associated with the I/O device is mapped by the second non-persistent memory is not contiguous with other addresses in the first non-persistent memory to which the second non-persistent memory maps.