US 11,698,841 B2
Integrated circuit chip with cores asymmetrically oriented with respect to each other
Jasbir Singh Nayyar, Bangalore (IN); Shashank Srinivasa Nuthakki, Telangana (IN); Rahul Gulati, Bangalore (IN); and Arun Shrimali, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jan. 27, 2022, as Appl. No. 17/585,979.
Application 17/585,979 is a continuation of application No. 16/838,176, filed on Apr. 2, 2020, granted, now 11,269,742.
Application 16/838,176 is a continuation of application No. 15/991,127, filed on May 29, 2018, granted, now 10,649,865, issued on May 12, 2020.
Application 15/991,127 is a continuation of application No. 14/854,900, filed on Sep. 15, 2015, granted, now 10,002,056, issued on Jun. 19, 2018.
Prior Publication US 2022/0147424 A1, May 12, 2022
Int. Cl. G06F 11/16 (2006.01); G06F 11/00 (2006.01); H01L 49/02 (2006.01); G06F 30/39 (2020.01); H01L 23/00 (2006.01)
CPC G06F 11/16 (2013.01) [G06F 11/004 (2013.01); G06F 11/1641 (2013.01); G06F 30/39 (2020.01); H01L 28/00 (2013.01); G06F 11/1679 (2013.01); H01L 23/562 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a first core having an output and a first orientation on a substrate;
a second core having an output and a second orientation on the substrate, wherein the second core is a replica of the first core and wherein the second orientation is different than the first orientation; and
a compare unit having a first input and a second input on the substrate, the first input coupled to the output of the first core and the second input coupled to the output of the second core, wherein the IC is formed with a microfabrication technique on a scale of 45 nanometers (nm) or smaller.