US 11,698,835 B2
Memory and operation method of memory
Munseon Jang, San Jose, CA (US); Hoi Ju Chung, San Jose, CA (US); and Jang Ryul Kim, San Jose, CA (US)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on May 25, 2021, as Appl. No. 17/329,681.
Claims priority of provisional application 63/080,850, filed on Sep. 21, 2020.
Claims priority of provisional application 63/042,230, filed on Jun. 22, 2020.
Prior Publication US 2021/0397515 A1, Dec. 23, 2021
Int. Cl. G11C 29/42 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01)
CPC G06F 11/1076 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for operating a memory, comprising:
reading data and an error correction code from a memory core;
correcting an error of the read data based on the read error correction code to produce error-corrected data;
generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion;
generating a new error correction code based on the new data;
writing the new data and the new error correction code into the memory core when a first mode is set; and
writing the write data portion of the new data and the new error correction code into the memory core when a second mode is set.