US 11,698,834 B2
Memory system
Kengo Kurose, Tokyo (JP); Masanobu Shirakawa, Chigasaki (JP); and Marie Takada, Yokohama (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Apr. 12, 2022, as Appl. No. 17/718,969.
Application 17/718,969 is a continuation of application No. 17/092,054, filed on Nov. 6, 2020, granted, now 11,334,432.
Application 17/092,054 is a continuation of application No. 16/550,355, filed on Aug. 26, 2019, granted, now 10,866,860, issued on Dec. 15, 2020.
Claims priority of application No. 2019-051530 (JP), filed on Mar. 19, 2019.
Prior Publication US 2022/0245030 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/26 (2006.01)
CPC G06F 11/1068 (2013.01) [G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method of controlling a semiconductor memory, the semiconductor memory including a word line and a plurality of memory cells connected to the word line, each of the memory cells being capable of storing n bit data, n being an integer equal to or larger than 2; the method comprising:
storing n pages of data in the memory cells;
reading data of a first page of the n pages as first data using a first voltage;
performing error correction on the first data;
calculating a first shift amount based on a first number and a second number, the first number representing a number of bits each of which has different values in a first manner between the first data and first expected data obtained by the error correction on the first data, the second number representing a number of bits each of which has different values in a second manner between the first data and the first expected data; and
reading data of a second page of the n pages as second data using a second voltage and a second shift amount, the second shift amount being based on the first shift amount.