US 11,698,832 B2
Selective sampling of a data unit during a program erase cycle based on error rate change patterns
Harish R Singidi, Fremont, CA (US); Ashutosh Malshe, Fremont, CA (US); Vamsi Pavan Rayaprolu, San Jose, CA (US); and Kishore Kumar Muchherla, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Aug. 30, 2021, as Appl. No. 17/461,918.
Application 17/461,918 is a continuation of application No. 16/862,446, filed on Apr. 29, 2020, granted, now 11,106,532.
Prior Publication US 2021/0390016 A1, Dec. 16, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 12/0882 (2016.01); G06F 11/30 (2006.01); G06F 12/02 (2006.01)
CPC G06F 11/1068 (2013.01) [G06F 11/076 (2013.01); G06F 11/0793 (2013.01); G06F 11/3037 (2013.01); G06F 12/0246 (2013.01); G06F 12/0882 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
determining a first error rate associated a first set of pages of a plurality of pages of a data unit of a memory device, and a second error rate associated with a second set of pages of the plurality of pages of the data unit;
determining a first pattern of error rate change for the data unit based on the first error rate and the second error rate; and
responsive to determining that the first pattern of error rate change corresponds to a predetermined second pattern of error rate change, performing an action pertaining to defect remediation with respect to the data unit.