US 11,698,787 B2
Interruptible and restartable matrix multiplication instructions, processors, methods, and systems
Edward T. Grochowski, San Jose, CA (US); Asit K. Mishra, Hillsboro, OR (US); Robert Valentine, Kiryat Tivon (IL); Mark J. Charney, Lexington, MA (US); and Simon C. Steely, Jr., Hudson, NH (US)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 29, 2021, as Appl. No. 17/362,854.
Application 17/362,854 is a continuation of application No. 16/398,200, filed on Apr. 29, 2019, granted, now 11,048,508.
Application 16/398,200 is a continuation of application No. 15/201,442, filed on Jul. 2, 2016, granted, now 10,275,243, issued on Apr. 30, 2019.
Prior Publication US 2021/0326131 A1, Oct. 21, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/3001 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30145 (2013.01); G06F 9/3861 (2013.01); G06F 9/3865 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a decode unit to decode an instruction, the instruction to indicate a first location of a first source matrix, to indicate a second location of a second source matrix, and to indicate a third location where a result matrix is to be stored; and
an execution unit coupled with the decode unit, the execution unit, in response to the decoded instruction, to:
break the first source matrix into a plurality of non-overlapping matrices and break the second source matrix into a plurality of non-overlapping matrices;
perform operations on the plurality of non-overlapping matrices from the first source matrix and the plurality of non-overlapping matrices from the second source matrix to generate the result matrix; and
store the result matrix in the third location.